1. Field of the Invention
The present invention relates to a multi-port memory with a plurality of input/output ports.
Priority is claimed on Japanese Patent Application No. 2008-71461, filed Mar. 19, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
Conventionally, DRAMs with a multi-port and multi-bank configuration, and control systems therefor are known.
For example, a conventional semiconductor storage apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. H08-221319 (Patent Document 1). This semiconductor storage apparatus has: a plurality of memory banks capable of storing data; and a plurality of input/output ports allowing input/output of data. Patent Document 1 discloses a multi-port RAM that couples the plurality of input/output ports to the memory banks via different buses.
Furthermore, a conventional semiconductor memory apparatus and a conventional information processing apparatus are disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-215659 (Patent Document 2). The semiconductor memory apparatus and the information processing apparatus include: m banks including a memory cell region where memory cells are arranged, a row selection circuit for selecting a row in the memory cell region, and a column selection circuit for selecting a column in the memory cell; and n ports. Patent Document 2 discloses an SDRAM provided with a multi-port circuit capable of accessing optional n banks from the n ports independently and simultaneously, where m≧n.
Furthermore, a conventional semiconductor storage apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. 2002-197858 (Patent Document 3). This semiconductor storage apparatus includes: external N ports each of which receives a command; N sets of buses, each corresponding to each of the external ports; a plurality of memory blocks connected to the N sets of buses; an address comparison circuit for comparing addresses accessed by a plurality of commands that are each input from the external N ports; and a determination circuit for determining, when the address comparison circuit detects accesses to the same memory block through the address comparison, which command is to be executed and which command is not to be executed among the commands that access the same memory block. Patent Document 3 discloses a multi-port DRAM including this semiconductor storage apparatus.
Furthermore, a conventional memory control circuit is disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-263363 (Patent Document 4). This memory control circuit includes: a plurality of ports that are connected to a plurality of independently accessible memory units; selectors that allocate ports to be accessed based on an apportion bit, the apportion bit being a predetermined bit in a memory access request address from each of a plurality of masters; arbitration devices that arbitrate memory access requests from the plurality of masters, the memory access requests being allocated by the selectors each connected to each port; and access devices that control a signal for accessing a memory according to contents of the memory access request of the master determined by the arbitration device connected to each of the ports. Patent document 4 discloses an SDRAM with this memory control circuit.
Furthermore, a conventional semiconductor storage apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-272378 (Patent Document 5). This semiconductor storage apparatus includes: a cell array made of volatile memory cells and including a plurality of banks; a plurality of external ports each capable of accessing independent addresses of the cell array; an arbitration circuit that determines order of access among the plurality of external ports; and a control circuit that outputs a busy signal to one of the plurality of the external ports if one bank is executing a core operation at the time of access request from the one port. Patent Document 5 discloses a DRAM type multi-port memory including this semiconductor storage apparatus.
Furthermore, a conventional multi-port random access memory is disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-346715 (Patent Document 6). This multi-port random access memory includes a plurality of memory banks, a plurality of buses, and a selection mechanism. This selection mechanism is connected to every memory bank in the plurality of memory banks and to every bus in the plurality of buses. The selection mechanism selects any memory bank from the plurality of memory banks to connect to any bus from the plurality of buses. Patent Document 6 discloses a multi-port RAM system with this multi-port random access memory.
Furthermore, a conventional multi-port semiconductor memory apparatus with a variable access route and a method thereof are disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-172811 (Patent Document 7). This multi-port semiconductor memory includes: a plurality of input/output ports different from one another; a memory array divided into a plurality of memory regions different from one another; and a selection control circuit for variably controlling access routes between the memory regions and the input/output ports so that each of the memory regions is accessed via at least one of the input/output ports.
Furthermore, a conventional multi-port internally cached DRAM is disclosed in Published Japanese translation No. 2001-511559 of the International Publication (Patent Document 8). This multi-port internally cached DRAM includes a multi-port internally cached DRAM array. A plurality of system I/O resources are connected via common internal data buses connected to corresponding DRAM cores in each unit of the array. One system I/O resource as a source of transmission writes a message in the internal DRAM cache array. Next, this message is read and simultaneously transferred to all the system I/O resources that are required to receive this message.
Patent Documents 1 to 8 disclose DRAMs with a multi-port and multi-bank configuration, and control methods and systems thereof In Patent Documents 1 to 8, a problem as follows occurs when with a plurality of banks allocated to a plurality of CPU cores via a plurality of input/output ports, data transfer load of an input/output port exceeds the limit of the data transfer capability during the period of time when a data transfer of another input/output port is not performed. That is, a problem occurs in that it is not possible to integrate a data signal line of an input/output port where no transfer is performed into a data signal line of an input/output port where the data transfer capability has exceeded the limit, to thereby dynamically improve the data transfer capability.
On the other hand, a conventional multi-port internally cached dynamic random access memory system is disclosed in Published Japanese translation No. 2000-501524 of the International Publication (Patent Document 9). This multi-port internally cached dynamic random access memory system is for use in a system having a master controller having parallel ports and a DRAM each connected for access to a common bus interface. The multi-port internally cached dynamic random access memory system includes a multi-port internally cached DRAM. This internally cached DRAM includes a plurality of independent serial data interfaces each connected between a separate external I/O resource and internal DRAM memory through corresponding buffers. A switching module is interposed between the serial interfaces and the buffers. In addition, the internal cache DRAM is controlled by the master bus controller so that a switching module logic dynamically makes a route between the serial interfaces and the buffers. Thus, there is disclosed a multi-port DRAM system that configures an input/output port by integrating one or more of the serial interfaces according to the external I/O resources, the system being capable of varying the number of serial interfaces according to the types of the external I/O resources.
However, with the technique disclosed in Patent Document 9, the number of the serial interfaces that are integrated according to the types of the external I/O resources is fixed for every system. As a result, a problem occurs when with a plurality of banks allocated to a plurality of CPU cores via a plurality of input/output ports, data transfer load of an input/output port exceeds the limit of the data transfer capability during the period of time when a data transfer of another input/output port is not performed. That is, a problem occurs in that it is not possible to integrate a data signal line of an input/output port where no transfer is performed into a data signal line of an input/output port where the data transfer capability has exceeded the limit, to thereby implement a function of dynamically improving the data transfer capability.
Furthermore, a conventional random access semiconductor memory apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. H05-342856 (Patent Document 10). In this random access semiconductor memory apparatus, there is provided an independent read/write control circuit for every data input/output terminal. Patent Document 10 discloses a random access memory that allows a partial read of data by use of some of a plurality of data input/output terminals or a simultaneous execution of a read of data by use of some of a plurality of data input/output terminals and a write of data by use of the others of the data input/output terminals. However, Patent Document 10 does not disclose a technique of accessing a plurality of CPU cores via a plurality of input/output ports.
Furthermore, a conventional SAM having an extendable data width for a multi-port RAM is disclosed in Published Japanese translation No. H10-511208 of the International Publication (Patent Document 11). The SAM includes a multi-port memory with SAM portions where a data width is adjustable. However, the technique disclosed in Patent Document 11 is for adjusting data widths of the SAM portions and the RAM portion. This poses a problem in that it is not possible to adjust a data transfer capability between a plurality of input/output ports.
Furthermore, a conventional semiconductor integrated circuit apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-243079 (Patent Document 12). Patent Document 12 discloses a technique of DRAM with a cache where a plurality of DRAM banks and an SRAM array are integrated. However, in the technique disclosed in Patent Document 12, the SRAM portion has two sets of input/output lines but has only one set of ports for performing a data transfer with the outside of the chip. This poses a problem in that it is not possible to adjust a data transfer capability between a plurality of banks and a plurality of input/output ports.
As described above, in a DRAM with a multi-port and multi-bank configuration of a conventional technique, when with a plurality of banks allocated to a plurality of CPU cores via a plurality of input/output ports, data transfer load of an input/output port exceeds the limit of its data transfer capability, it was not possible to integrate a data signal line of an input/output port where no transfer is performed into a data signal line of an input/output port where the data transfer capability has exceeded the limit, to thereby dynamically improve the data transfer capability.